Thermal management of vertical GaN transistors

This study analyzes the thermal management strategies of novel vertical GaN-membrane devices, which are produced on foreign substrates. The thermal conductivity of the GaN layered structures grown on silicon as well as on sapphire are investigated by scanning thermal microscopy and time domain thermoreflectance. These data are then used in a thermal simulation to determine the thermal behavior of different device designs. Based on that, it is found that the primary heat dissipation path starts with the lateral spreading within the GaN layers and then goes through the die attach to the board. This reveals also the thermal importance of the die attach on the whole system. The results suggest that it is possible to develop such GaN membrane-based devices with a thermal resistance of < 1 K/W, which is necessary to maintain a reliable operation also in high-power applications.