Area Efficient Reliable QCA Adder and Subtractor

Adders and Subtractors are the key computational circuits. Quantum-dot Cellular Automata adders and subtractors are implemented by using combination of 3-and 5-input majority logic. In some cases, they are constructed by using dedicated exclusive-or gates. The nano scale circuits are more prone to fabrication defects. But in the current scenario, less importance is given to the defect tolerance ability of the circuits. The gates and inverters are the key components of the circuits and the defect tolerance ability of them determine the reliability of the circuit. Hence, the fault percentage of them must be small for reliable circuits. Reliability is achieved by increasing the size of gates and inverters. But it increases the circuit size and delay. Reliable QCA adders and subtractors are proposed in this work with smaller area compared to existing designs realized using fault tolerant gates. Realization of higher word length designs using proposed designs is validated by realizing an 8-bit adder and subtractor. Verification is done in QCADesigner.