Design and Analysis of 16-bit Vedic Multiplier Using UT Sutra of Vedic Mathematics

Multipliers play a vital part in today's Digital Signal Processing systems. Low power and high-speedsystems are implemented in majority of the applications. Hence, power dissipation is targeted nowadays in digital communications. Multiplication in normal mathematics can be a tedious process, so multipliers can find it difficult to calculate. This paper presents the working of a multiplier that uses the ancient Vedic mathematics called the “Urdhva Tiryakbhyam” sutra. The work is done with a
$2\mathrm{x}2$
, a
$\boldsymbol{4}\mathbf{x}\boldsymbol{4}$
, an
$\boldsymbol{8}\mathbf{x}\boldsymbol{8}$
, and a
$\boldsymbol{16}\mathbf{x}\boldsymbol{16}$
bit multiplier. Performance analysis of the Vedic multiplier is carried out. Detecting the correct value for delay and power was a challenge in this paper. However, delay and power are analyzed and discussed further, giving a good result compared to previous constructions.