A high performance JPEG2000 architecture

JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination required in the present wireless and internet age. These features are possible due to adaptation of discrete wavelet transform, intra-subband bit plane coding and binary arithmetic coding. All the three algorithms are complex and require substantial number of memory accesses. In this paper we propose a system level architecture capable of encoding and decoding using the JPEG2000 core algorithm. The key components include dedicated architectures for wavelet, bit plane and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18 /spl mu/ technology, is 3 mm square and the estimated frequency of operation is 200 Mhz.