Design of oversampling current steering DAC with 640 MHz equivalent clock frequency

Recent mobile communications demand high-speed and high-resolution data converters for digital signal processing (DSP) in the receiver and transceiver of the communication systems. Those applications require more than 14-bit resolution and several hundred of MHz bandwidth. In this paper, we propose a new sigma-delta parallel DAC (Digital-to-Analog Converter) structure that achieves the required accuracy with 640 MHz clock frequency. The circuit employs current steering and multi-bit solution with matching technique. The entire architecture has been verified by simulations with a 0.18 /spl mu/m CMOS process (TI).