A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

This letter presents an analog layout generator-based digital LDO (DLDO) with a self-triggered binary search windowed flash analog-to-digital conversion (ADC) in 22-nm CMOS. A self-triggered binary search mechanism with a delay-based architecture is proposed to reduce the exponentially growing kickback noise and energy consumption of a traditional flash ADC down to the level of a SAR ADC while maintaining its high-speed feature. To conquer the complexity bottleneck of SoC development in FinFET technology, a practical analog layout generation framework is proposed to maximize the productivity of implementing analog circuit blocks in the scaled CMOS process. To meet the performance, area and reliability specifications across a variety of circuits, the methodology allows varying levels of constraints from designers, thus significantly improving the physical design time & effort up to
$60\times $
compared with conventional manual approach. The DLDO features 3.55-ps FoM and fully automatic generation.