FPGA Implementation of High Performance Hybrid Encryption Standard

Now a day's data hacking is the main issue for cloud computing, protecting a data there are so many methods in that one most usable method is the data Encryption. Process of Encryption is the converting a data into an un readable form using encryption key, encoded version that can only be read with authorized access to the decryption key. This paper presenting a simple, energy and area efficient method for endurance issue in secure resistive main memories. In this method, by employing the random characteristics of the encrypted data encoded by the Advanced Encryption Standard (AES) as well as a rotational shift operation. Random Shifter is simple hardware implementation and energy efficient method. It is considerably smaller than that of other recently proposed methods. Random Shifter technique used for secure memory with other error correction methods. Due to their reprogram ability, Field Programmable Gate Arrays (FPGA) are a popular choice for the hardware implementation of cryptographic algorithms. The proposed random shifter algorithm for AES and DES (Hybrid) data is implemented in the VIRTEX FPGA and it is efficient and suitable for hardware-critical applications. This Paper is implemented using model sim and Xilinx 14.5 version.