FPGA Implementation of Division Algorithm for SVPWM

Field programmable gate array (PFGA) has advantages of parallel processing, fast operation, and high reliability. Therefore, it has broad application prospects in high-performance servo drives. As an indispensable operation in the space vector pulse width modulation (SVPWM) algorithm for permanent magnet synchronous motor (PMSM), division is the most complex among the four operations. When implemented in FPGA, it will consume the most logic resources and generate the longest latency. According to the characteristics of the division algorithm in SVPWM, this paper proposes an improved design method for the universal divider. Through the improvement of the division design, less resource consumption and shorter latency are realized.