Design of Ultra Low Power 6T SRAM Cell Using 180 nm CMOS Technology for Access Enhancement

The low power IC design has been a priority because of the recent growth in battery-operated portable devices. With the advancement in microcircuit technology, a low power, low transistor count and faster enhancement of static random-access memory (SRAM) has proved to be essential. Therefore, in such embedded systems, parallel read/write (R/W) access multiport SRAM bit-cells are the need of the hour. This area of SRAM design, along with CMOS technology, is being scaled up in different system-on-chip (SoC) products. In this paper, a 256-bit SRAM design is proposed using 180nm CMOS technology along with its peripheral circuits like 6 transistor (6T) cells, pre-charge circuit, write driver, column and row decoders, sense amplifiers, etc. in such a way that its operation speed is high compared to the other conventional SRAM cells. Our proposed SRAM has a speed of 12ns compared to other conventional SRAM's speed of about 400ns, which is way faster.