Modeling Insights Into the Assembly Challenges of Focal Plane Arrays

Ongoing technological advances in photodetector material growth and processing, readout integrated circuits, and robust hybridization (packaging) methods for assembling high-resolution and small-pitch size pixel arrays are the main enabling factors for pushing the frontiers of high-performance Focal Plane Array (FPA) technologies for imaging systems. This paper details the development of analytical and numerical models and demonstrates their use to generate insights into the feasibility of two flip-chip assembly processes for packaging infrared (IR) detector chips. The modeling studies focus on the challenges of forming the indium interconnection arrays in the case of the FPA technologies using Group III-V compound semiconductor materials and ultra-fine pitch pixel array layouts. The accurate alignment of the IR detector chip onto the readout chip in the case of high-density pixel architectures is a critical requirement for the packaging process. To gain a better understanding of this requirement, which has a clear implication for the quality and subsequent reliability performance of the FPA, compression, and reflow bonding process models are developed using suitable modeling approaches and methods and then demonstrated for two distinctive focal plane array design configurations. The novelty of this work is in the developed modeling capabilities utilizing different computational methods, from large deformation and contact analysis finite element to energy-based and harmonic motion mechanics, to characterize and optimize the mechanical and dynamic non-linear behavior of the indium solder joints and their formation during FPA packaging. The feasibility of bonding techniques for different resolution FPAs and under flip-chip misalignment conditions is assessed. The modeling results pointed to a very strict, sub-micrometer flip-chip placement accuracy requirement for the assembly of FPAs with ultra-fine indium bump array resolution.