High-Throughput Polynomial Multiplier for Accelerating Saber on FPGA

Saber was once one of the most promising candidates for the post-quantum cryptography standardization, which relies on lattice-based hard mathematical problems. Polynomial multiplication is time-consuming within the Saber architecture and there is still a lack of designs targeting the high throughput applications whose parameters support Schoolbook polynomial multiplier. In this brief, we propose a high-performance Schoolbook polynomial multiplier with a balanced hardware efficiency. The Schoolbook algorithm is transformed into a Toeplitz matrix-vector product, and its symmetry is exploited to reconstruct the Schoolbook multiplier to satisfy the need for high parallelism. Combined with compact data loading structure and a centralizing multiplication, the multiplier achieves
$3.33\times $
higher throughput and
$1.58\times $
higher throughput-per-slice compared with the state-of-the-art implementation of polynomial multiplier for Saber on Xilinx FPGA. The experimental results also demonstrate that the proposed structure provides a better trade-off between performance and area.