Low Voltage Squarer/Divider Circuit based on FGMOS

A low voltage squarer/divider (SD) circuit based on floating gate MOS (FGMOS) technique has been presented. Twofold MOS translinear loop (MTL) biased in saturation region has been used to design the proposed SD circuit. This work utilizes the threshold voltage tunability property of FGMOS and MTL for realizing a low voltage SD circuit in saturation region. Full wave rectifier (FWR) has also been designed for analog signal processing applications using the proposed SD circuit. Simulations have been conducted on Cadence VIRTUOSO software using 180nm gpdk technology at VDD =0.7V. The simulation results show that the proposed SD circuit offers maximum error of 3.5% for an input range of $\pm 35\mu$A, static and maximum power consumption of 35.36$\mu$W and 64.72$\mu$W and -3dB bandwidth is 190. 54MHz. Simulation results of FWR indicate that maximum percentage of deviation from linearity is 11% for an input range of $\pm 35\mu$A, static and maximum power consumed is 1.SS$\mu$W and 115.4$\mu$W and -3dB bandwidth is 17. 37MHz. Moreover, the sensitivity of the proposed circuits in the practical environment has been validated using corner analysis at all the process corners and has been tested and verified for a wide range of temperatures.