Design and Implementation of Arithmetic based FIR Filters for DSP Application

In real life applications the signals are continuously captured, monitored, processed and analysed. The pro cessing and analysis of data is easier if it is in the form of digital. The Digital Signal Processing (DSP) finds importance mainly in biomedical devices or wearable devices. In DSP system, the Finite Impulse Response (FIR) filter design acts as a basic building block. In wearable applications where the complex computation is involved, to acquire high accuracy the filters with higher order is used. The Multipliers is heart of any filter design, accommodates major chip area and require extra time for computation. The designers mainly concentrate on the optimization of multiplier over the existing one. An attempt is made in this paper to design FIR filter based on Distributed Arithmetic (DA) algorithm which is mainly depends on the precomputed values stored in the Look-Up Tabe(LUT). It is a multiplier less design architecture. It is observed that the distributed arithmetic-based architecture is efficient for real signal computation. The paper highlights the advantages of DA technique over the traditional MAC based design. Both the desig
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are coded in Verilog and verified for the functionality and comparison is made. The proposed design has given area, power and timing advantauc of 64%.62% and 61% respectively.