Research on Chip Level Inspection and Maintenance System of Electronic Products under Computer Digitization

In this paper, a fixed fault model is established, and a digital chip tester is designed with HT46RU24 as the core. The FPGA+SDRAM high performance hardware processing platform is built according to the high efficiency of FPGA parallel processing. Using Quartus II software and Verilog HDL hardware description language to write a program to detect the edge of chip pins. In this paper, a chip detection algorithm based on generalized Hough transform is proposed to reduce the computational complexity. The main idea of this algorithm is to combine multi-scale analysis with generalized Hough transform. The algorithm is applied to the chip detection of automatic optical detection system. Then the system controls and tests the operation of the hardware through the test code and compares the test results with the exact values. The simulation results show that the system can automatically give the result of right or wrong judgment.