A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture

Deep neural networks (DNN) have been widely used in many real-time artificial intelligent (AI) applications because of effective hardware accelerators. However, most present designs either suffer from high area cost or low hardware usage. This paper presents a design of a digital logic accelerator (DLA) for use in PBs (processing block) of an opto-electrical neural network (OENN). The proposed DLA uses processing elements that detects underflow and overflow. Besides, it also increased the processing time to resolve the timing problems. The details of the design together with post-layout simulations are presented in this paper. The DLA is implemented using a typical 40-nm CMOS process. It showed a performance result of 51.2 GOPS and the power consumption is 91.3 mW at 125 MHz.