Fast Simulation of Analog Spiking Neural Network With Device Non-Idealites

We present a method for spiking neural network simulation with hardware realistic device non-idealities present in the neuron and synapse circuits as an alternative to time-consuming spice simulation. Neuromorphic machine learning algorithms for spiking neural networks are often simulated with an ideal mathematical description of spiking neurons and synapses. However, silicon implementations of spiking neurons differ significantly from their ideal mathematical models because of device non-idealities and restrictions in the range of device operation. These non-idealities affect the performance of chip implementations of spiking networks. The dynamical system phase plane of the neuron and synapse circuit is used to create a compact representation of the neuron dynamics that captures device non-idealities for simulation of spiking neural networks. The proposed method would allow hardware-aware optimization of neuromorphic algorithms using standard machine learning tools and provide simulated network prediction close to what would be expected from a chip implementation.