Testability Design and Testability Rating for Better Built In Test

GENERAL COMMENTSThis paper discusses an overall process of Built In Test design and a FMECA based BIT Effectiveness analysis that both endorses a more informative BIT architecture and design, and leverages a Failure Mode, Effects, and Criticality Analysis (FMECA) with complimentary Built-In-Test Effectiveness (BEA) for the evaluation and ultimately compliance with BIT effectiveness requirements.. The purpose of the Testability Design and Testability Rating System is to address some best practices for how to design BIT into a system that creates a more useful BIT system, and other best practices for improvements to how BIT requirements are stated or developed, that can result in a more fair and honest rating for a design’s inherent testability.The (continued) transformation of the project Reliability/Maintainability (R/M) engineer/analyst’s role is a key recommendation of this paper. To achieve higher performance BIT systems which can also result in increased user satisfaction that the BIT system correctly indicates issues that are important (critical) to the end user operator/maintainer, there needs to be increased expectations to grow the role of R/M Engineer to assume the subject matter expert responsibilities of a Diagnostics and Prognostics System Architecture &/Requirements Engineer. This is distinctly different from a designer who traditionally is most interested in meeting the performance requirements asked for the design, and the Test Engineer who is traditionally primarily looking for ways to fully cover all functions or components of the design to assure proper operation of the unit prior to shipment [9]. This increased expectation of the traditional R/M Role bridges several important potential voids in the system design. That being;1. Understanding what is critical and not critical to operation.2. The methods and tools to "score" the design accurately for BIT Effectiveness, and thereby guide BIT design choices.3. The opportunity to bridge to an improved Supportability posture over the deployed lifetime by adding BIT design features to enhance possible availability, Diagnostic, Prognostic and Health Management capabilities of the design.