A 99.22% Energy-saving and 86.91% Area-reduction Capacitor Switching Scheme for SAR ADCs

This paper proposes an energy-saving and area-reduction capacitor switching scheme for successive approximation analog-to-digital converters (SAR ADCs). The switching scheme combines top-plate sampling technology, a novel switching method and the MSB capacitor splitting technology to eliminate the power consumption of the first two conversion cycles. In addition, there is no energy consumption during the reset phase. This switching scheme reduces the area of the DAC capacitor array through C-2C technology. Compared with the traditional switching scheme, the proposed scheme achieves an area reduction of 86.91%. For the first N-1 conversion cycles of an N-bit SAR ADC, the positive and negative capacitor arrays of the proposed switching scheme switch symmetrically. The common mode voltage remains constant. LSB conversion cycle, positive and negative capacitor arrays are switched unilaterally. The 10-bit SAR ADC of the proposed switching scheme is modeled and simulated by MATLAB. The results show that 99.22% switching energy saving is achieved compared with the traditional switching scheme.