Dead-Time Impact on the Harmonic Distortion and Conversion Efficiency in a Three-Phase Five-Level Cascaded H-Bridge Inverter: Mathematical Formulation and Experimental Analysis

To avoid leg short-circuit in inverters, dead time must be introduced on leg gate signals. Dead time affects the inverter output voltage fundamental harmonic amplitude, voltage harmonic distortion and inverter efficiency by introducing additional voltage drops. In this regard, dead time effects have been widely investigated for traditional two-level three-phase voltage source inverters in the literature but not extensively for multilevel topology structures. This paper provides a detailed analysis of dead time impact on the harmonic distortion and efficiency of Cascaded H-Bridges Multilevel Inverters (CHBMIs). For this purpose, a general mathematical formulation to determine voltage drop due to dead time effects, also taking into account the adopted Multicarrier PWM strategy, has been provided and experimentally validated for a five-level three-phase CHBMI structure. As a comparison tool between expected and ideal inverter output voltage, the percentage voltage error
$e_{\%}$
is introduced. In most of the cases,
$e_{\%} $
is lower than 5%, and it starts increasing for very low amplitude modulation index or for specific working points where nonlinearities occur. Furthermore, several experimental investigations have been carried out to evaluate the CHBMI performance in terms of harmonic distortion and efficiency by changing, the values of dead time, modulation index and switching frequency for ten different multi-carried PWM strategies. Experimental results confirm the strong dependency between the dead time impact on the converter performance and the adopted Multi Carrier-PWM (MC-PWM) strategy: as a way of example, converter efficiency can be reduced from 80% to 60% when dead time is increased from
$0.5 \mu \text{s}$
to
$1.5 \mu \text{s}$
and Phase Shifted-PWM (PS-PWM) is adopted.