Digital column readout architecture for the ATLAS pixel 0.25 /spl mu/m front end IC

A fast, low noise, limited power, radiation-hard front-end chip was developed for reading out the ATLAS pixel silicon detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified in order to allow a safe transition to quarter micron technology and overcome any possible situation where single point defects and charge deposited by heavy ions in the silicon could have lead to unpredicted forbidden states. Moreover, the smaller feature sizes and the higher speed of these processes allowed us to enhance the design of the basic blocks and adopt a fail safe, design for testability approach.