Architectural Improvement and Performance Evaluation of 1D-to-2D Array Conversion Priority Encoder

Priority Encoders (PE) are essential component in time critical applications like interrupt controller and CAM and are useful in fields like image processing, on-chip testing applications and computer architecture optical communication. In this paper, we have used PE design using the 1D array to 2D array conversion method to implement 4-bit, 16-bit, and 64-bit PEs. This method is used because of its scalability and huge advantage in saving time. We have implemented structural improvements in the 1-D to 2-D array architecture using the 180nm CMOS process. For PE at 64-bit operating at a voltage of 1V, our design provides a 63% improvement in transistor count and an 88.09% improvement in operating frequency as compared with the reported work.