An Improved Design of Low Power High Speed Configurable Logic Block using 90nm CMOS Technology

Configurable Logic Block (CLB) is the basic computational component of FPGA. The existing methods of creating CLB suffer from temperature sensitivity, higher static and switching power consumption, high clock latency from numerous clocks, increased propagation delay, incompatible process technology with state of the art etc. This paper aims to form a low power design of CLB with minimized propagation delay and clock latency, less layout area and more compatible process technology than the existing ones. The overall architecture is created using Verilog code in EDA playground as well as Cadence Virtuoso with 90nm process technology. Three input majority function with the Boolean logic,
$\mathrm{F}= \mathrm{A}.\mathrm{B}+\mathrm{B}.\mathrm{C}+\mathrm{A}.\mathrm{C}$
is implemented with the proposed CLB. The functionality is checked and the performance of the CLB is evaluated by different design matrices. Various performance parameters such as active energy, leakage energy, maximum operating frequency etc. have been measured to be 9.123fJ, 1.148fJ and 100MHz respectively. The maximum propagation delay (79.27ps) ∼ and the power efficiency (
$1.505\mu \mathrm{W}$
) ∼ have been calculated by Virtuoso Wave calculator. Finally, the optimized physical layout is obtained, which renders minimum area of
$233.91\ \mu\mathrm{m}^{2}$
, resulting in highly compact integration of transistors.