Design of Random Number Sequence Generator using Multi-Stage Feedback with Multi-Stage Ring Oscillator

TRNGs, or true random number generators, are crucial to VLSI testing. This article proposes a unique approach for producing real random numbers on an FPGA using the entropy source is the unpredictable jitter of an MSFRO (multi-stage feedback ring oscillator). The traditional ring oscillator is modified by a multi-stage feedback mechanism that increases the entropy source's randomness, frequency, and range of clock jitter. We sample the phase-locked loop (PLL) of the FPGA's clock signal using the clock jitter signal generated by the MSFRO, in contrast to the traditional clock sampling structure. The collected output value is processed by XOR to decrease the variance and increase the unpredictability. MSFRO are offered to show how well the suggested Low Power BIST method performs. Verilog HDL will be used to implement this proposed design, and Modelsim Tool will be used to simulate it. The FPGA Spartan 3 XC 3S 200 TQ 144 and Xilinx Synthesis are the proposed MSFRO.