VLSI Design of Majority Logic based Wallace Tree Multiplier

By using the Wallace Tree multipliers architecture and improving the adder in each Wallace Tree phase, reduce the unnecessary latency. The dominant logic primitive was used for addition since it functions more effectively than NAND/NOR/IMPLY primitives. By executing several majority gates with in node columns, a high amount of circuit parallelism is utilized at the array level. These have an impact on the in-memory multiplier delay, which surpasses all other in-memory multipliers that have been previously reported. The proposed Majority Gates were developed in Verilog, modelled in Simulation 6.4c, and then synthesized using the Xilinx Tool.