A Nonlinear Dead-Time Compensation Strategy Based on Current Prediction for High-Capacity Cascaded H-Bridge Test System

Cascaded h-bridge (CHB) is a widely used topology for high-power applications and is considered the development trend of high-voltage power converters because of its advantages, such as fewer output harmonics, smaller filter size, and easier modularization. However, the dead-time effect will introduce low harmonics to the output voltage, which filters cannot eliminate well. This paper proposes a nonlinear dead-time compensation strategy to reduce harmonics and voltage distortions in cascaded H-bridge test systems. With accurate modeling of the existing system, this approach derives the short-circuit current in transformer testing based on precise calculation of the output harmonics. It predicts the zero-crossing point of the current and then fully considers the effects of the sampling and transmission delay to obtain the threshold current for dead-time compensation. This method can solve the voltage distortion caused by dead-time and transmission delay. Finally, simulation results in a three-phase 25-level cascaded H-bridge converter verify the excellent performance of the proposed method.