Wire Length-Matching Aware Placement Method for Rapid Single Flux Quantum Logic Circuits

This paper proposes a fast automatic gate placement method for gate-level-pipelined Rapid Single Flux Quantum (RSFQ) circuits that are designed to have a high throughput. In such circuits, the gates in a pipeline stage are placed in a column and wires are routed in the area between adjacent columns. In wire routing, wire length-matching is performed. The proposed method performs gate placement for a given netlist to minimize the sum of the maximum distance between connected gates in each pair of adjacent columns. It leads to short wire extensions in wire length matching for increasing the operation frequency and small circuit area. The proposed method consists of a recursive procedure including two placements, selecting a pivot column, and determining the gate placement in the pivot column. The netlist is divided into two netlists with the pivot column. The recursive procedure performs gate placements for the two divided netlist. It is repeated until the location of every gate is determined. We implemented a placement tool by the proposed method and performed the gate placement for three circuits including several hundreds of gates. The proposed placement was 14 to 40 times faster than a placement based on simulated annealing where the sum of the maximum distance between connected gates is approximately the same.