Design of a Modified Current Starved Inverter Based Ring Oscillator for Switched Capacitor Circuit

Now a day's Switched capacitor circuits (SC) are widely used in different signal processing blocks such as Filters and ADCs due to its lower power consumption and lesser area. The design of switch capacitor circuit requires a non-overlapping clock and an oscillator. In this paper a novel inverter is proposed which is used for designing an oscillator. for low power and frequency clock generation. The proposed inverter consists of a cascaded current starved inverter and a current starved inverter connected in inverted fashion. The proposed design is simulated in Cadence Virtuoso using GPDK 90nm. The simulation result of the proposed inverter block gives a 866 ps delay which is nearly 40% more than the conventional design. The designed oscillator with a 51 MHz frequency consumes a power of 100.6 µW., which is nearly thrice less than the conventional design.