Analysis of Parasitic Inductance in Multi-MHz Frequency Switching Power Converters

Minimizing the parasitic inductance is crucial for high-frequency switching applications such as 4G/5G envelope tracking. Decoupling capacitors are typically used to reduce the noise from the power supply and maintain signal integrity. When several capacitors are placed in parallel, the parasitic inductance estimation becomes challenging. In this paper, an analysis of the parasitic inductance and effective current loop is carried out using ANSYS Q3D simulation. Several capacitors are considered as the source of excitation and the parasitic inductance information are extracted. The simulated results are used to estimate the ringing frequency at the switch node and to compare with the values obtained from experiments performed on the fabricated PCBs with the same design. Based on the results, the effective current loop and the most critical capacitor(s) are determined. Such information can significantly improve the PCB designs for multi-MHz converters via the optimization of the parasitic inductances.