Investigation on the impact of External Layout-dependent Gate-Drain Capacitance on the Switching Dynamics of Si SJMOS

The external parasitic gate-drain capacitance is a constant capacitance that exists between the externally accessible gate and drain terminals of the power MOSFET, and it is contributed by the layout of the gate and drain nodes routed in the PCB. Due to its comparable magnitude with the internal gate-drain capacitance of the silicon superjunction MOSFETs, it can significantly affect the switching dynamics during the voltage-rise and voltage fall periods. This effect is even more pronounced for superjunction MOSFET with low current rating. In this work, a quantitative investigation of the impact of the parasitic gate-drain capacitance o the switching dynamics is presented and verified experimentally for a wide operating condition for a 650V and 12A silicon superjunction MOSFET.