Parallel Acceleration of Real-time Feature Extraction Based on SURF Algorithm

Visual feature extraction is the key to target registration calculation. Compared with SIFT, SURF feature extraction algorithm has less computational complexity and better applicability when image signal-to-noise ratio is low. In this paper, an FPGA-based SURF algorithm for real-time feature extraction and parallel acceleration is designed for large-field scene registration applications of space targets. Firstly, the application scenario of space target is analyzed, and the grayscale features of the data containing the target used for registration are counted. Then, the five main parts of SURF algorithm were analyzed, and the algorithm was simplified based on the gray feature of the image. Finally, according to the simplified results, the parallel pipeline architecture of each module is designed based on FPGA. SURF computing modules are also given in this paper the design of the architecture and data flow of information, in XC7K325 completed the whole design of experiment, the results show that the design for 1024 × 1024 pixel image, single frame image processing time need only 51 us, resource usage is not more than 18.6%, power consumption is not more than 7.5 W, The computational efficiency is 87% higher than the previous design. Low signal-to-noise ratio (SNR) was used to simulate space target scene data for simulation test calculation, and the SURF descriptor error was less than 3%, ensuring the system's calculation error while effectively utilizing resources.