Comparative analysis of TG FinFET and GAA FinFET in 3 nm technology node

Leakage current and Short Channel Effects (SCE) are the main barriers in the progress of FinFET device manufacturing. The miniaturization of the channel length introduces some problems like the increase of the threshold voltage, the increase of power dissipation in CMOS circuits and the decrease of the ON current of the FinFET device. Researchers have innovated a new structure called the GAA FinFET in order to improve the performance of the device. The 3-D geometry of FinFET structures imposes new challenges which are essential for the choice of the appropriate transport model for nanoscale device in advanced technology nodes. This paper presents a comparative analysis of 3 nm Trigate (TG) FinFET and Gate All Around (GAA) FinFET. Its aim is to present a higher performance device for better CMOS circuits application.