A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

DAC mismatch is a major challenge for high-resolution ADCs. This brief proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm2 and consumes
$0.656~\mu \text{W}$
under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.