A 17.5-to-21-GHz Current-Folding Frequency Tripler With >36-dBc Harmonic Rejection in 90-nm CMOS

In this letter, a current-folding frequency tripler (FT) is presented to convert the fundamental input into the triple-frequency output. To demonstrate FT operation, we built in a voltage-controlled oscillator (VCO) to generate the fundamental signal and used a bandpass stage for harmonic suppression. Fabricated in the 90-nm CMOS technology, the core consumes 5 mW from 1.2-V supply. When the measured tuning range of VCO is from 5.83 to 7 GHz, the FT features 36 to 43-dBc fundamental harmonic rejection from 17.5 to 21 GHz. The phase noise of the FT at 18.96 GHz is −102.8 dBc/Hz at 1-MHz offset while the VCO is with −112.5 dBc/Hz.