Design and Implementation of Best Master Clock Selection Algorithm Based on FPGA

With the rapid innovation of aerospace technology, aerospace-oriented TSN (Time Sensitive Network, TSN) network technology has been rapidly developed, among which the Best Master Clock Selection Algorithm (BMCA) is the guarantee of the TSN network clock Foundation. In this paper, on the basis of the analysis of the time synchronization protocol, the BMCA in the protocol is an analyzed, designed and implemented, and a system for implementing the BMCA with full hardware logic is proposed. This design uses two ZYNQ7020 boards as master-slave nodes. Through behavior simulation and timing simulation verification, the selection of the best master clock between the master-slave nodes is realized.