Gray Code Arithmetic for Clock Domains Transfer

Modern high-speed FPGA and VLSI often operate using multiple clock subnets (synchronization domains). It is necessary to solve the problem of reliable data transfer between different clock domains. For this purpose, we should minimize the number of simultaneously changing bits within the clock stability window. A well-known mathematical model aimed to solve this problem is the usage not of binary notation to form address pointers but Gray’s code, specially designed to meet such kind of requirements.The classical approach for arithmetics in Gray code is to use conversion from Gray code to binary code, use binary arithmetic operations and convert the result back from binary code to Gray code. We propose new algorithms for such arithmetic operations which are free of conversions from Gray code to binary code.