A Configurable Inter-chip Connection Architecture for Multicore Neuromorphic Chip

As the spiking neural network model structure becomes more and more complex, the single-chip neuromorphic processor can no longer meet the bandwidth and computing resource requirements of the SNN model and applications, which has become the bottleneck of neuromorphic computing. Besides, the current chip interconnection method does not apply to neuromorphic chips because of the large transmission delay. Therefore, we propose a switch to support multi-chip neuromorphic processor interconnection. Multiple chips are interconnected through the switch, and each core uses routers to connect to intra-chip cores. To evaluate the performance, a 100 MHz FPGA prototype of our inter-chip connection architecture was implemented. The experimental results show that our inter-chip connection architecture can reduce the latency of data packet transmission by 1.5× compared with the previous work.