Review and Analysis on Network on Chip

Moore's law has been extended with the introduction of multiprocessor architectures and platforms. To boost design productivity and system performance, they leverage concurrency and synchronisation in both software and hardware. Furthermore, these systems must be highly scalable, reusable, and repeatable. They'll also have to be low-cost and low-energy. It is expected that deep sub-micron technology, defined by gate lengths of 60–90 nm, will be plagued by wire delays, signal integrity issues, and unsynchronized communications as billion transistors age. The important developments in NOC research are discussed, as well as aspects that demand more exploration. The most widely used and researched topology is a packet-switched 2-D mesh. It's also a bit of an average NoC right now. There are lots of positive outcomes and intriguing proposals. However, there were significant discrepancies in implementation results, ambiguous documentation, and a lack of comparability.