A massively parallel GP engine in VLSI

In this paper we propose the implementation of a massively parallel genetic programming (GP) model in hardware in order to speed up the genetic algorithm. This fine-grained diffusion architecture consists of a large amount of independent processing nodes that evolve a large number of small, overlapping subpopulations. Every node has an embedded CPU that executes a linear machine code GP representation at a rate of up to 20,000 generations per second.