Detailed Modeling and In-Situ Calorimetric Verification of Three-Phase Sparse NPC Converter Power Semiconductor Losses

The three-phase (3-
$\Phi $
) three-level (3-L) sparse neutral point clamped converter (SNPCC) combines a 3-L matrix stage and a 3-
$\Phi $
two-level (2-L) inverter stage to generate 3-L switched output voltages with a reduced transistor count (10 instead of 12 or 18) compared with the classical 3-L NPCC or 3-L active NPCC structure, targeting variable-speed drive (VSD) systems with low ripple of the motor phase currents or bidirectional 3-
$\Phi $
power factor correcting (PFC) rectifier systems with reduced boost inductor volume. This article analyzes and experimentally characterizes the performance of an IGBT-based 3-
$\Phi 3$
-L SNPCC and describes, for the first time, a hybrid current commutation effect between inverter-stage diodes and matrix-stage IGBTs that occurs when operating with lower modulation indices and leads to increased switching losses (up to
${20}{\%}$
). The proposed new semiconductor loss modeling approach accounts for this effect successfully, which is verified (
$< {10}{\%}$
error) on an 800-
${\text {V}}_{\text {dc}}$
, 7.5-kW SNPCC hardware demonstrator using a new in-situ calorimetric method that facilitates accurate stage-level semiconductor loss measurements. Heat spreading effects caused by the asymmetrical losses injection and thermal decoupling between two in-situ loss measurement blocks are carefully checked with finite-element method (FEM) simulations. Furthermore, an experimental evaluation of common-mode (CM) and differential-mode (DM) high-frequency (HF) voltage-time area ripples (as a generic measure for the required filtering effort) for three typical symmetrical and asymmetrical modulation switching state sequences is provided together with the semiconductor loss characterization. Utilizing a low-switching-loss asymmetric modulation scheme that operates the 3-L matrix stage and the 2-L inverter stage with the effective switching frequencies of 16 kHz and 5.3 kHz, respectively, the 3-L SNPCC demonstrator finally achieves a high rated power (7.5 kW, load current phase shift
$\phi = 0$
) semiconductor efficiency of 98.8%.