A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization

Ever-growing applications, such as 5G communication, deep learning, advanced driver-assistance systems (ADAS), and extended reality (XR), have fueled demand for increased computing power and per-pin interface bandwidth. Recently, four-level pulse-amplitude modulation (PAM4) has been adopted as a solution [1-3]: the throughput is doubled without increasing the baud (Nyquist) rate. Compared to a conventional non-return-to-zero (NRZ) signaling, PAM4 requires more design effort: varying from the precise design of I/O circuits to the off-chip characterization. This is in part due to SNR degradation and an increased switching jitter (SWJ). For a
$1^{\text{st}}$
-order low-pass filter with a Nyquist-frequency cutoff, SWJ is 35% for the middle eye and 51.2% for the top and bottom eyes [4]. Maximum-transition-avoidance (MTA) encoding [3] can be used to reduce SWJ, but at the cost of additional encoder/decoder hardware and an auxiliary channel to compensate for data loss.