10.6 A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer

Many
$\text{IoT}$
applications demand ADCs with high resolution, medium bandwidth, and good energy efficiency. Lately, the incremental ADC is drawing
^r
ising attention by favoring system integration with its easy multiplexing and simple digital filtering. By combining a low-power SAR with a low-distortion
$\Delta\Sigma$
modulator, the zoom architecture achieves high energy efficiency and high resolution simultaneously [1–2]. However, the conventional zoom ADC can only convert quasi-static signals, since the two stages operate sequentially, and its
$\Delta\Sigma$
conversion operates at a slow speed. The dynami
^c
zoom architecture performs coarse and fine conversions concurrently, thus being able to convert varying inputs [3–4]. Yet, limited by the low quantization level of the fine
$\Delta\Sigma \mathrm{M}$
, it requires a large OSR for the targeted resolution (e.g., 282.25 in [3] and 87.5 in [4]), which restricts the input bandwidth to several tens of
$\text{kHz}$
, Moreover, its loop filter relies on charge transfer, where each conversion requires dedicated sampling for its residue generation. As a result, in addition to the limited input bandwidth, the largely repeated sampling operation incurs extra power and design challenge for input drivers. The CT zoom architecture features easy driving while still requiring a large conversion cycle of 8192 in [5]. Recently, the emerging noise-shaping (NS) SAR ADC employs the efficient SAR for the multi-bit quantizer, significantly reducing conversion cycles [6–7]. However, without the initial coarse quantization, high loop filter orders are usually required for hig h -resolution applications, raising significant hardware cost and design complexity.