A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET

In hyper scale data centers, high-speed links beyond 100Gb/s are required by applications such as XSR (co-packaged optics and die-to-die interconnects) or LR (ethernet switches, ASICs, and retimers). This work presents a 112Gb/s LR SerDes system with a DSP-based PAM-4 transceiver for large-scale switching ASICs (25.6∽51.2Tb/s). For a compact and low-cost system configuration, each lane is recommended to drive more than 40dB channel loss [1–4] without repeaters. Maximum heat capacity of a package comprising a die with hundreds of transceiver lanes imposes a strict limit on the maximum power consumption per lane. In addition, large-scale integration leads to noisy operating conditions due to Xtalk and supply noise. Concurrent supports of multiple standard specifications (for example Ethernet and Fibre Channel) require independent lane speed as well as lane swapping. This flexible clocking requirement can be solved by utilizing a TX-PLL and an RX-PLL per lane [4]. However, electromagnetic (EM) coupling between inductors in neighboring lanes is a challenge, especially when an LC oscillator is necessary for low-jitter clocking. This work overcomes those challenges by using a low-power and long-reach DSP-based transceiver with careful modeling of aggressive ASIC impairments on sensitive circuits.