17.5 A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor

Next-generation wireless standards (e.g., WiFi-7) advancing towards wider bandwidth and higher order modulation require ADCs with GHz sampling rates and over 12b resolution. Although conventional pipelined ADCs can satisfy the speed and resolution specifications, their power is usually too high for handset applications, for which
$\leq 10\text{mW}$
per channel is desired. Alternatively, time-interleaved (TI) ADCs achieve low power by harnessing efficient low-speed SAR sub-ADCs. However, background timing-skew calibrations bring considerable overhead and place limitations on the input signal. The pipeline/TI-SAR hybrid architecture places the interleaved SAR at the
$2^{\text{nd}}$
pipeline stage to avoid the timing skew problem [1]. As the SAR consumes low power and can run asynchronously, this greatly reduces the pipeline backend power and simplifies the clock distribution. However, the residue amplifier is still a power efficiency bottleneck as in a conventional pipeline. In [1], the architecture advantages are shaded by its power-hungry telescopic OTA. This work proposes a ring amplifier with split MDAC to boost the efficiency of the pipelined TI-SAR architecture, which enables a 1GS/s 10-ENOB ADC which consumes only 6.9mW. For high-speed ADCs, the power and area overhead of the reference buffer is also a critical issue. This work proposes a reference decoupling capacitor (de-cap) switching technique that reduces the reference buffer power to only 3.7mW, and the total de-cap size to only 44pF, while maintaining excellent high-frequency performance. Overall, this work achieves
$\text{FoM}_{\mathrm{s}}$
of 171.1 and 169.2dB with or without the reference buffer, which outperforms all reported works with
$\mathrm{f}_{\mathrm{s}} > 600\text{MS}/\mathrm{s}$
.