6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

The ever-increasing demand for greater I/O bandwidth has pushed the transceiver data rate to 200Gb/s [1]. At this rate, the implementation of decision-feedback equalizers faces severe timing constraints. Discrete-time feed-forward equalizers (FFEs) in receivers (RXs) break the timing loop and compensate for electrical and optical impairments [2–3]. However, it relies on accurate, multiphase, and high-speed sampling clocks. The RX FFEs implemented in the continuous-time domain use active [4–5] or passive [5–6] delay lines, which eliminate clock and interleaved sample-and-hold circuits. In addition, the continuous-time FFE preserves edge information and therefore supports the oversampling clock and data recovery (CDR). This paper presents a 5-tap delay-line-based receiver FFE operating at 200Gb/s and equalizing a 17.2dB-loss channel.