33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference

Emerging non-volatile memory-based computing-in-memory (CIM) is an excellent fit for resource-constrained edge-AI devices [1–6]. MRAM-CIM macros for MAC operations, at present, rely on a crossbar structure or a peripheral circuit modification [2], [3]. It remains a great challenge for bottom-up design of MRAM-CIM macro using the standard one transistor - one magnetic tunnel junction (1T-1MTJ) bit-cell: (1) The mainstream spin-transfer-torque (STT) switching mechanism with a standard foundry bit-cell cannot fulfill CIM operation requirements in binary neural networks (BNN). (2) The excessive multi-row/column activation method suffers from a limited read window due to the limited tunnel magnetoresistance ratio and process variation [1], [2]. (3) Prior MRAM-CIMs rely on analog domain computing, for which an analog-to-digital converter is required with it's associated high energy consumption and area overhead [3], [6].