An 8-bit 3.5 GS/s Current Steering DAC for Wireless Applications

A segmented 8-bit 3.54 GS/s current-steering digital-to-analog converter (CSDAC) designed and simulated in 130 nm CMOS technology. The spurious-free dynamic range (SFDR) that represents the CSDAC linearity is ranged from 65.7 dB at 11 MHz signal frequency to 54 dB at 1.770 GHz with an effective number of bits (ENOB) equals to 7.97 bits at a low frequency while degraded across the input frequency to reach 7.67 bit at 1.77 GHz.