Analog Triggered Asynchronous Clocking Technique Based on the Ring Amplifier in Pipeline ADC

A design technique for the analog triggered asynchronous clocking control technique for the pipeline ADC is presented, which is convenient for the realization of highly integrated ADCs. The analog trigger technique is implemented with dynamic-power residue amplifiers such as ring amplifiers (RAMPs) inside ADC to generate the ready signal, so the asynchronous processing is realized, which solves the design problem of establishing a high-frequency clock inside the highly integrated ADCs and completes the low-power designs. Simulation results of the adopted fully-differential RAMP using 130nm CMOS process models, supply of 1.2V, and clock frequency of 200MHz. Compared with the ready signal generated by the dynamic comparator in the SAR ADC, the results show that the duty cycle generated by the RAMP is 50%, and the setting up time is 114.1ps, which is more suitable for high-speed design.