The Design of Multipliers Based on Radix-4 Booth Coding

For the multiplication processing rate of the chip arithmetic unit, a 32-bit pipelined multiplier is designed, which can be used in a reconfigurable array processor designed by the author. The Multiplier applies the Radix-4 Booth coding algorithm, optimizes the circuit of partial product generation, and compresses the partial product by using the Wallace tree. A 32-bit Radix-4 Booth-coded addition tree is optimized for reconfigurable array processors synthesizing 3-2 and 4-2 compressors and the Wallace tree is divided into three levels. The pipeline register is inserted in each level, which improves the speed of partial product operation. Through analysis and simulation, the multiplier reduces the gate delay and improves the multiplication speed of chips.