An IEEE-Compatible JTAG Test-Access-Port Controller for RSFQ Logic and Systems

JTAG, an IEEE-standard test protocol, is widely used for testing commercial and experimental CMOS chips but appears unused for testing superconducting chips. The test-access-port (TAP) controller described here facilitates the use of JTAG to reduce the cost – in time and effort – of testing superconductive circuits. Our RSFQ-based TAP controller shifts data serially through a scan chain that transfers data in parallel to and from a circuit under test. Suitably designed scan chains can provide initial values to superconducting circuits and retrieve results to explore circuit behavior. A control computer or an internet connection can operate our TAP controller through a simple five-wire interface. Our TAP controller implements the TAP part of IEEE standard 1149.8.1-2012 in an area of only 580 × 280 micrometers, less area than two bonding pads. Our TAP Controller design information and MIT SFQ5ee layout will be freely available.