Delay Enhancement of Wallace Tree Multiplier with Binary to Excess-1 Converter

In this paper, a modified Wallace tree multiplier with several adders is presented. In every microprocessor and DSP circuit, the multiplier performs a vital function. The delay in multipliers is caused by the operating speed constraints of adders; by replacing standard adders with advanced adders in the multiplier’s design, the total latency in the formation of partial products may be drastically decreased. In terms of memory and delay, the Wallace tree multiplier and the array multiplier are investigated. As wallace multiplier is preferable than array multiplier, the Wallace multiplier’s construction is proposed utilizing Kogge Stone Adder (KSA) and carry select adder (CSLA) with Binary to Excess-l converter (BEC). The findings demonstrate that the suggested multiplier with BEC is effective, with minimal latency and memory use. The suggested wallace multiplier is implemented in Verilog and simulated in XILINX. The multiplier performance is validated using the Spartan 3E FPGA package. The designed multiplier is highly desirable for high-speedapplications.